Circuit designers of multi-Gigabit systems face a number of challenges as advances in technology mandate increased performance in high-speed components. For example, chip-to-chip data rates have traditionally been constrained by the bandwidth of input/output (IO) circuitry in each component. However, process enhancements (e.g., transistor bandwidth) and innovations in IO circuitry have forced designers to also consider the effects of the transmission channels between the chips on which data is sent.
At a basic level, data transmission between components within a single semiconductor device or between two devices on a printed circuit board may be represented by the system 100 shown in FIG. 1. In FIG. 1, a transmitter 102 (e.g., a microprocessor) sends data over channel 104 (e.g., a copper trace on a printed circuit board or “on-chip” in a semiconductor device) to a receiver 106 (e.g., another processor or memory). When data is sent from an ideal transmitter 102 to a receiver 106 across an ideal (lossless) channel, all of the energy in a transmitted pulse will be contained within a single time cell or unit interval (UI).
However, real transmitters and real transmission channels do not exhibit ideal characteristics, and as mentioned above, the effects of transmission channels are becoming increasingly important in high-speed circuit design. Due to a number of factors, including, for example, the limited conductivity of copper traces, the dielectric medium of the printed circuit board (PCB), and the discontinuities introduced by vias, the initially well-defined digital pulse will tend to spread or disperse as it passes over the transmission path. This is shown in FIG. 2A. As shown, a single pulse of data 105a is sent by the transmitter 102 during a given UI (e.g., UI3). However, because of the effect of the channel 104, this data pulse becomes spread 105b over multiple UIs at the receiver 106, i.e., some portion of the energy of the pulse is observed outside of the UI in which the pulse was sent (e.g., in UI2 and UI4). This residual energy outside of the UI of interest may perturb a pulse otherwise occupying either of the neighboring UIs, in a phenomenon referred to as intersymbol interference (ISI).
ISI is shown more succinctly in the simulation of FIG. 2B. Shown are two ideal pulses, π1 and π2, each occupying their own adjacent unit intervals. The resulting dispersed pulses, P1 and P2, represent simulated received versions of the ideal pulses after transmission at 10 Gb/s through a 6-inch copper trace in a standard printed circuit board material (FR4). The dispersion in each of these pulses overlaps the other pulse, as shown by the hatched portions in the drawings, which represent ISI. The larger pulse, P3, represents the waveform that results when P1 and P2 are sent across the same channel with no intermediate delay, which is a common occurrence in the standard non-return-to-zero (NRZ) signaling format.
Because ISI can give rise to sensing errors at the receiver 106, a number of solutions have been proposed to offset or compensate for the effects of ISI. On the transmitter 102 side, a filter 108 may be employed to compensate for the anticipated effects of the channel 104. Such a filter 108, which can comprise an equalizer, attempts to pre-condition the transmitted signal such that the effect of the channel 104 is removed. One skilled in the art will appreciate that the terms “equalizer,” “equalization filter,” “filter,” etc., may be used interchangeably in this regard. One such technique comprises the use of finite-impulse response (FIR) filters. See, e.g., R. W. Lucky et al., “Automatic equalization for digital communication,” in Proc. IEEE, vol. 53, no. 1, pp. 96-97 (January 1965); R. W. Lucky and H. R. Rudin, “Generalized automatic equalization for communication channels,” in Proc. IEEE, vol. 53, no. 3, pp. 439-440 (March 1966); S. Reynolds et al., “A 7-tap transverse analog-FIR filter in 0.13 μm CMOS for equalization of 10-Gb/s fiber-optic data systems,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 330-331 (February 2005); M. E. Said et al., “A 0.5-μmSiGe pre-equalizer for 10-Gb/s single-mode fiber optic links,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 224-225 (February 2005); and J. E. Jaussi et al., “8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 80-88 (January 2005); all of which are incorporated herein by reference in their entireties. Such an FIR filter 108 performs processes known as pre-emphasis or de-emphasis in which the signal is intentionally pre-distorted before it is transmitted to compensate for the anticipated effects of the channel 104. An FIR filter 108 may alternatively be employed on the receiver side 106 (not shown) to compensate for effects of the channel. Unfortunately, FIR filters typically require multiple taps to compensate for the losses in a channel, resulting in larger, more power-hungry, and more complicated circuitry.
Alternatively, on the receiver 106 side, an equalizer implemented in circuitry 109 may be used to compensate for the effects of the channel 104, including ISI. The transfer function of an ideal equalizer is the inverse of the transfer function of the channel 104, and a practical equalizer attempts to recreate this inverse frequency response. One such ISI-mitigating technique includes the use of decision feedback equalization (DFE) circuitry 109 at the receiver 106 side of the transmission. See, e.g., M. E. Austin, “Decision-feedback equalization for digital communication over dispersive channels,” Massachusetts Institute of Technology: Research Laboratory of Electronics, Cambridge, Tech. Rep. 461 (1967); M. Sorna et al., “A 6.4-Gb/s CMOS SerDes core with feedforward and decision-feedback equalization,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 62-63 (February 2005); R. Payne et al., “A 6.25-Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 68-69 (February 2005); J. W. M. Bergmans, “Digital magnetic recording systems,” IEEE Trans. Magn., vol. 24, pt. 1, pp. 683-688 (January 1988); J. E. C. Brown et al., “A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording,” IEEE J. Solid-State Circuits, vol. 34, no. 2, pp. 162-169 (February 1999); and R. S. Kajley et al., “A mixed-signal decision-feedback equalizer that uses a look-ahead architecture,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 450-459 (March 1997); all of which are incorporated herein by reference in their entireties. DFE presents an attractive solution as it is fairly resistant to high-frequency noise amplification, and further provides a variable detection threshold that may be designed to follow shifts or trends in data resulting from ISI. However, DFE is more difficult to implement than an FIR filter in the multi-Gigahertz frequency range due to the necessary reliance on feedback from past decisions.
A third filtering option comprises continuous-time equalization, which is implemented by circuitry 109 at the receiver 106 side of the transmission. See, e.g., B. K. Casper et al, “A 20 Gb/s Forwarded Clock Transceiver in 90 nm CMOS,” Proceedings of the IEEE International Solid State Circuit Conference, San Francisco, Calif., pp. 263-272 (February 2006); Y. Tomita et al., “A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 986-993 (April 2005); and H. Higashi et al., “A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 978-985 (April 2005), all of which are incorporated herein by reference in their entireties. While continuous-time filters contribute very little to a system in terms of power, noise, and jitter, they are more difficult to tune. Moreover, the performance of an adaptive equalizer, such as a traditional continuous-time equalizer, is limited by process variations inherent in printed circuit board fabrication; such variations limit the precision with which a chip-to-chip channel may be formed (trace impedance, spacing, length matching, etc.), and thus, limit the amount or accuracy of compensation an equalizer may provide. While process variations lead to some variation in a channel, a major challenge related to continuous-time filters and equalizers is the process variance in the equalizer circuits themselves. The frequency response of a continuous-time equalizer cannot be expected to fit the intended design initially due to process and environmental variability, and thus, calibration is necessary not only to optimize the equalizer to a specific channel, but also to compensate for the non-idealities of the equalizer circuits themselves.